View LTC3548IDDTRPBF_6425610.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc3548 1 3548fc typical application features applications description pdas/palmtop pcs digital cameras cellular phones portable media players pc cards wireless and dsl modems n high ef? ciency: up to 95% n very low quiescent current: only 40a n low output ripple burst mode ? operation n 2.25mhz constant-frequency operation n high switch current: 0.7a and 1.2a n no schottky diodes required n low r ds(on) internal switches: 0.35 n current mode operation for excellent line and load transient response n short-circuit protected n low dropout operation: 100% duty cycle n ultralow shutdown current: i q < 1a n output voltages from 5v down to 0.6v n power-on reset output n externally synchronizable oscillator n small thermally enhanced msop and 3mm 3mm dfn packages dual synchronous, 400ma/800ma, 2.25mhz step-down dc/dc regulator the ltc ? 3548 is a dual, constant-frequency, synchronous step down dc/dc converter. intended for low power ap- plications, it operates from 2.5v to 5.5v input voltage range and has a constant 2.25mhz switching frequency, allowing the use of tiny, low cost capacitors and inductors with a pro? le 1mm. each output voltage is adjustable from 0.6v to 5v. internal synchronous 0.35, 0.7a/1.2a power switches provide high ef? ciency without the need for external schottky diodes. a user selectable mode input is provided to allow the user to trade-off noise ripple for low power ef? ciency. burst mode operation provides high ef? ciency at light loads, while pulse-skipping mode provides low noise ripple at light loads. to further maximize battery runtime, the p-channel mosfets are turned on continuously in dropout (100% duty cycle), and both channels draw a total quiescent cur- rent of only 40a. in shutdown, the device draws <1a. figure 1. 2.5v/1.8v at 400ma/800ma step-down regulators run2 v in v in = 2.8v to 5.5v v out2 = 2.5v at 400ma v out1 = 1.8v at 800ma run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3548 10f 100k reset 33pf 68pf 2.2h 4.7h 887k 604k 301k 280k 4.7f 10f 3548 ta01 load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 power loss (mw) 1000 100 10 1 0.1 10 100 1000 3548 ta02 v in = 3.3v, v out = 1.8v burst mode operation channel 1, no load on channel 2 power loss efficiency ltc3548 ef? ciency curve l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6127815, 6304066, 6498466, 6580258 6611131..
ltc3548 2 3548fc lead free finish tape and reel part marking* package description temperature range ltc3548edd#pbf ltc3548edd#trpbf lbnj 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc3548idd#pbf ltc3548idd#trpbf lbnj 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc3548emse#pbf ltc3548emse#trpbf ltbnh 10-lead plastic msop C40c to 85c ltc3548imse#pbf ltc3548imse#trpbf ltbnh 10-lead plastic msop C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ v in voltages .................................................C 0.3v to 6v v fb1 , v fb2 voltages ...........................C 0.3v to v in +0.3v run1, run2 voltages ................................ C 0.3v to v in mode/sync voltage .......................C 0.3v to v in + 0.3v sw1, sw2 voltage ...........................C 0.3v to v in + 0.3v por voltage .................................................C 0.3v to 6v (note 1) operating temperature range (note 2)....C 40c to 85c junction temperature (note 5) ............................. 125c storage temperature range ...................C 65c to 125c lead temperature (soldering, 10 sec) mse only .......................................................... 300c absolute maximum ratings pin configuration order information electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.6v, unless otherwise speci? ed. (note 2) symbol parameter conditions min typ max units v in operating voltage range l 2.5 5.5 v i fb feedback pin input current l 30 na v fb feedback voltage (note 3) 0c t a 85c C40c t a 85c l 0.588 0.585 0.6 0.6 0.612 0.612 v v v linereg reference voltage line regulation v in = 2.5v to 5.5v (note 3) 0.3 0.5 %v top view dd package 10-lead (3mm s 3mm) plastic dfn 10 11 9 6 7 8 4 5 3 2 1 v fb2 run2 por sw2 mode/ sync v fb1 run1 v in sw1 gnd t jmax = 125c, ja = 45c/w, jc = 3c/w exposed pad (pin 11) is pgnd, must be connected to gnd (soldered to a 4-layer board) top view 1 2 3 4 5 v fb1 run1 v in sw1 gnd 10 9 8 7 6 v fb2 run2 por sw2 mode/ sync 11 mse package 10-lead plastic msop t jmax = 125c, ja = 45c/w, jc = 10c/w exposed pad (pin 11) is pgnd, must be connected to gnd (soldered to a 4-layer board)
ltc3548 3 3548fc electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3548 is guaranteed to meet speci? ed performance from 0c to 85c. speci? cations over the C 40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3548i is guaranteed to meet speci? ed performance over the full C40c to 85c temperature range. note 3: the ltc3548 is tested in a proprietary test mode that connects v fb to the output of the error ampli? er. note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: t j is calculated from the ambient t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja ). note 6: the dfn switch on-resistance is guaranteed by correlation to wafer level measurements. the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.6v, unless otherwise speci? ed. (note 2) symbol parameter conditions min typ max units v loadreg output voltage load regulation (note 3) 0.5 % i s input dc supply current active mode sleep mode shutdown (note 4) v fb1 = v fb2 = 0.5v v fb1 = v fb2 = 0.63v, mode/sync = 3.6v run = 0v, v in = 5.5v, mode/sync = 0v 700 40 0.1 950 60 1 a a a f osc oscillator frequency v fb = 0.6v l 1.8 2.25 2.7 mhz f sync synchronization frequency 2.25 mhz i lim peak switch current limit channel 1 peak switch current limit channel 2 v in = 3v, v fb = 0.5v, duty cycle <35% v in = 3v, v fb = 0.5v, duty cycle <35% 0.95 0.6 1.2 0.7 1.6 0.9 a a r ds(on) top switch on-resistance bottom switch on-resistance (note 6) (note 6) 0.35 0.30 0.45 0.45 i sw(lkg) switch leakage current v in = 5v, v run = 0v, v fb = 0v 0.01 1 a por power-on reset threshold v fb ramping down, mode/sync = 0v C8.5 % power-on reset on-resistance 100 200 power-on reset delay 262,144 cycles v run run threshold l 0.3 1 1.5 v i run run leakage current l 0.01 1 a mode mode threshold low mode threshold high 0 v in C 0.5 0.5 v in v v typical performance characteristics t a = 25c unless otherwise speci? ed. load step burst mode operation pulse-skipping mode 3548 g01 v in = 3.6v v out = 1.8v i load = 180ma channel 1; circuit of figure 3 sw 5v/div v out 20mv/div i l 200ma/div 2s/div 3548 g02 v in = 3.6v v out = 1.8v i load = 30ma channel 1; circuit of figure 3 sw 5v/div v out 10mv/div i l 200ma/div 1s/div 3548 g03 v in = 3.6v v out = 1.8v i load = 80ma to 800ma channel 1; circuit of figure 3 v out 200mv/div i l 500ma/div i load 500ma/div 20s/div
ltc3548 4 3548fc typical performance characteristics ef? ciency vs input voltage oscillator frequency vs supply voltage oscillator frequency vs temperature ef? ciency vs load current load regulation line regulation reference voltage vs temperature r ds(on) vs input voltage r ds(on) vs junction temperature t a = 25c unless otherwise speci? ed. input voltage (v) 2 3548 g04 3 456 100 95 90 85 80 75 70 65 60 efficiency (%) v out = 1.8v, channel 1 burst mode operation circuit of figure 3 800ma 10ma 100ma 1ma 2.5 2.4 2.3 2.2 2.1 2.0 frequency (mhz) temperature (c) C50 25 75 3548 g05 C25 0 50 100 125 v in = 3.6v 10 8 6 4 2 0 C2 C4 C6 C8 C10 frequency deviation (%) supply voltage (v) 2 3548 g06 3 456 0.615 0.610 0.605 0.600 0.595 0.590 0.585 reference voltage (v) temperature (c) C50 25 75 3548 g07 C25 0 50 100 125 v in = 3.6v v in (v) 1 500 450 400 350 300 250 200 46 3548 g08 2 3 57 r ds(on) (m) main switch synchronous switch t a = 25c junction temperature (c) C50 550 500 450 400 350 300 250 200 150 100 25 75 3548 g09 C25 0 50 100 150 125 r ds(on) (m) main switch synchronous switch v in = 3.6v v in = 4.2v v in = 2.7v load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3548 g11 v in = 3.6v, v out = 1.8v no load on other channel channel 1; circuit of figure 3 burst mode operation pulse-skipping mode load current (ma) 1 v out error (%) 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 10 100 1000 3548 g12 burst mode operation pulse-skipping mode v in = 3.6v, v out = 1.8v no load on other channel channel 1; circuit of figure 3 v in (v) 2 v out error (%) 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 4 6 3548 g15 35 v out = 1.8v i out = 200ma t a = 25c
ltc3548 5 3548fc v fb1 (pin 1): output feedback. receives the feedback voltage from the external resistive divider across the output. nominal voltage for this pin is 0.6v. run1 (pin 2): regulator 1 enable. forcing this pin to v in enables regulator 1, while forcing it to gnd causes regulator 1 to shut down. this pin must be driven; do not ? oat. v in (pin 3): main power supply. must be closely decoupled to gnd. sw1 (pin 4): regulator 1 switch node connection to the inductor. this pin swings from v in to gnd. gnd (pin 5): ground. this pin is not connected internally. connect to pcb ground for optimum shielding. mode/sync (pin 6): combination mode selection and oscillator synchronization. this pin controls the operation of the device. when tied to v in or gnd, burst mode operation or pulse-skipping mode is selected, respectively. do not ? oat this pin. the oscillation frequency can be synchronized to an external oscillator applied to this pin and pulse-skipping mode is automatically selected. sw2 (pin 7): regulator 2 switch node connection to the inductor. this pin swings from v in to gnd. por (pin 8): power-on reset . this common-drain logic output is pulled to gnd when the output voltage falls below C8.5% of regulation and goes high after 117ms when both channels are within regulation. run2 (pin 9): regulator 2 enable. forcing this pin to v in enables regulator 2, while forcing it to gnd causes regulator 2 to shut down. this pin must be driven; do not ? oat. v fb2 (pin 10): output feedback. receives the feedback voltage from the external resistive divider across the output. nominal voltage for this pin is 0.6v. exposed pad (gnd) (pin 11): power ground. connect to the (C) terminal of c out , and (C) terminal of c in . must be connected to electrical ground on pcb. pin functions typical performance characteristics ef? ciency vs load current ef? ciency vs load current ef? ciency vs load current t a = 25c unless otherwise speci? ed. load current (ma) 1 efficiency (%) 100 90 80 70 60 50 40 10 100 1000 3548 g10 3.6v 2.7v 4.2v v out = 2.5v, channel 1 burst mode operation no load on other channel circuit of figure 3 load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3548 g14 2.7v 4.2v v out = 1.5v, channel 1 burst mode operation no load on other channel circuit of figure 3 3.6v load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3548 g13 2.7v 4.2v v out = 1.2v, channel 1 burst mode operation no load on other channel circuit of figure 3 3.6v
ltc3548 6 3548fc block diagram the ltc3548 uses a constant-frequency, current mode architecture. the operating frequency is set at 2.25mhz and can be synchronized to an external oscillator. both channels share the same clock and run in-phase. to suit a variety of applications, the selectable mode pin allows the user to choose between low noise and high ef? ciency. the output voltage is set by an external divider returned to the v fb pins. an error ampli? er compares the divided output voltage with a reference voltage of 0.6v and adjusts the peak inductor current accordingly. an undervoltage comparator will pull the por output low if the output voltage is not above C8.5% of the reference voltage. the por output will go high after 262,144 clock cycles (about 117ms) of achieving regulation. 1 2 9 10 8 3 4 11 5 C + C + C + C + ea uvdet ovdet 0.6v 7 0.65v 0.55v C + 0.35v uv ov i th switching logic and blanking circuit s r q q rs latch burst C + i comp i rcmp anti shoot- thru burst clamp slope comp en sleep por counter 0.6v ref osc osc regulator 2 (identical to regulator 1) pgood1 pgood2 shutdown v in v in v in 6 regulator 1 sw1 gnd por gnd sw2 5 mode/sync v fb1 run1 run2 v fb2 3548 bd main control loop during normal operation, the top power switch (p-channel mosfet) is turned on at the beginning of a clock cycle when the v fb voltage is below the the reference voltage. the current into the inductor and the load increases until the current limit is reached. the switch turns off and energy stored in the inductor ? ows through the bottom switch (n-channel mosfet) into the load until the next clock cycle. the peak inductor current is controlled by the internally compensated i th voltage, which is the output of the error ampli? er.this ampli? er compares the v fb pin to the 0.6v reference. when the load current increases, the v fb voltage decreases slightly below the reference. operation
ltc3548 7 3548fc this decrease causes the error ampli? er to increase the i th voltage until the average inductor current matches the new load current. the main control loop is shut down by pulling the run pin to ground. low current operation by selecting mode/sync (pin 6), two modes are available to control the operation of the ltc3548 at low currents. both modes automatically switch from continuous operation to the selected mode when the load current is low. to optimize ef? ciency, the burst mode operation can be selected. when the load is relatively light, the ltc3548 automatically switches into burst mode operation, in which the pmos switch operates intermittently based on load demand with a ? xed peak inductor current. by running cycles periodically, the switching losses which are domi- nated by the gate charge losses of the power mosfets are minimized. the main control loop is interrupted when the output voltage reaches the desired regulated value. a voltage comparator trips when i th is below 0.35v, shutting off the switch and reducing the power. the output capaci- tor and the inductor supply the power to the load until i th exceeds 0.65v, turning on the switch and the main control loop which starts another cycle. for lower ripple noise at low currents, the pulse-skipping mode can be used. in this mode, the ltc3548 continues to switch at a constant frequency down to very low currents, where it will begin skipping pulses. the ef? ciency in pulse- skipping mode can be improved slightly by connecting the sw node to the mode/sync input which reduces the clock frequency by approximately 30%. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. in dropout, the pmos switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. an important design consideration is that the r ds(on) of the p-channel switch increases with decreasing input supply voltage (see typical performance characteristics). therefore, the user should calculate the power dissipation when the ltc3548 is used at 100% duty cycle with low input voltage (see thermal considerations in the applica- tions information section). low supply operation to prevent unstable operation, the ltc3548 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 1.65v. a general ltc3548 application circuit is shown in figure 2. external component selection is driven by the load requirement, and begins with the selection of the inductor l. once the inductor is chosen, c in and c out can be selected. inductor selection although the inductor does not in? uence the operating frequency, the inductor value has a direct effect on ripple current. the inductor ripple current i l decreases with higher inductance and increases with higher v in or v out : i l = v out f o ?l ?1? v out v in ? ? ? ? ? ? l v out f o ? i l ?1? v out v in(max) ? ? ? ? ? ? operation applications information
ltc3548 8 3548fc required. several capacitors may also be paralleled to meet the size or height requirements of the design. an additional 0.1f to 1f ceramic capacitor is also recommended on v in for high frequency decoupling, when not using an all ceramic capacitor solution. table 1. representation surface mount inductors part number value (h) dcr ( max) max dc current (a) size w l h (mm 3 ) sumida cdrh3d16 2.2 3.3 4.7 0.075 0.110 0.162 1.20 1.10 0.90 3.8 3.8 1.8 sumida cdrh2d11 1.5 2.2 0.068 0.170 0.900 0.780 3.2 3.2 1.2 sumida cmd4d11 2.2 3.3 0.116 0.174 0.950 0.770 4.4 5.8 1.2 murata lqh32cn 1.0 2.2 0.060 0.097 1.00 0.079 2.5 3.2 2.0 toko d312f 2.2 3.3 0.060 0.260 1.08 0.92 2.5 3.2 2.0 panasonic elt5kt 3.3 4.7 0.17 0.20 1.00 0.95 4.5 5.4 1.2 output capacitor (c out ) selection the selection of c out is driven by the required esr to minimize voltage ripple and load step transients. typically, once the esr requirement is satis? ed, the capacitance is adequate for ? ltering. the output ripple (v out ) is determined by: v out i l esr + 1 8f o c out ? ? ? ? ? ? inductor core selection different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar elec- trical characteristics. the choice of which style inductor to use often depends more on the price vs size requirements and any radiated ? eld/emi requirements than on what the ltc3548 requires to operate. table 1 shows some typi- cal surface mount inductors that work well in ltc3548 applications. input capacitor (c in ) selection in continuous mode, the input current of the converter is a square wave with a duty cycle of approximately v out /v in . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: i rms i max v out (v in ?v out ) v in where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple cur- rent, i max = i lim ? i l /2. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case is commonly used to design because even signi? cant deviations do not offer much relief. note that capacitor manufacturer?s ripple cur- rent ratings are often based on only 2000 hours lifetime. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than applications information
ltc3548 9 3548fc applications information tantalum capacitors are all available in surface mount packages. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr (size) product of any aluminum electrolytic at a somewhat higher price. special polymer capacitors, such as sanyo poscap , panasonic special polymer (sp), and kemet a700, of- fer very low esr, but have a lower capacitance density than other types. tantalum capacitors have the highest capacitance density, but they have a larger esr and it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors have a signi? cantly larger esr, and are often used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have the lowest esr and cost, but also have the lowest capacitance density, a high voltage and temperature coef? cient, and exhibit audible piezoelectric effects. in addition, the high q of ceramic capacitors along with trace inductance can lead to signi? cant ringing. in most cases, 0.1f to 1f of ceramic capacitors should also be placed close to the ltc3548 in parallel with the main capacitors for high frequency decoupling. ceramic input and output capacitors higher value, lower cost ceramic capacitors are now be- coming available in smaller case sizes. these are tempting for switching regulator use because of their very low esr. unfortunately, the esr is so low that it can cause loop stability problems. solid tantalum capacitor esr generates a loop zero at 5khz to 50khz that is instrumental in giving acceptable loop phase margin. ceramic capacitors remain capacitive to beyond 300khz and usually resonate with their figure 2. ltc3548 general schematic run2 v in v in = 2.5v to 5.5v v out2 v out1 run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3548 c in r5 power-on reset c4 c5 l1 l2 r4 r2 r1 r3 c out2 c out1 3548 f02 ps* bm* *mode/sync = 0v: pulse skip mode/sync = v in : burst mode esl before esr becomes effective. also, ceramic caps are prone to temperature effects which requires the designer to check loop stability over the operating temperature range. to minimize their large temperature and voltage coef? cients, only x5r or x7r ceramic capacitors should be used. a good selection of ceramic capacitors is available from taiyo yuden, avx, kemet, tdk and murata. great care must be taken when using only ceramic input and output capacitors. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v in pin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, the ringing at the input can be large enough to damage the part. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead ful? ll a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. typically, 3 to 4 cycles are required to respond to a load step, but only in the ? rst cycle does the output drop linearly. the output droop, vdroop , is usually about 2 to 3 times the linear drop of the ? rst cycle. thus, a good place to start is with the output capacitor size of approximately: more capacitance may be required depend- ing on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. a 10f ceramic capacitor is usually enough for these conditions. setting the output voltage the ltc3548 develops a 0.6v reference voltage between the feedback pin, v fb , and the ground as shown in figure 2. the output voltage is set by a resistive divider according to the following formula: v out = 0.6v 1 + r2 r1 ? ? ? ? ? ?
ltc3548 10 3548fc stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. to improve the frequency response, a feed-forward capaci- tor c f may also be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. power-on reset the por pin is an open-drain output which pulls low when either regulator is out of regulation. when both output volt- ages are above C8.5% of regulation, a timer is started which releases por after 2 18 clock cycles (about 117ms). this delay can be signi? cantly longer in burst mode operation with low load currents, since the clock cycles only occur during a burst and there could be milliseconds of time between bursts. this can be bypassed by tying the por output to the mode/sync input, to force pulse-skipping mode during a reset. in addition, if the output voltage faults during burst mode sleep, por could have a slight delay for an undervoltage output condition. this can be avoided by using pulse-skipping mode instead. when either channel is shut down, the por output is pulled low, since one or both of the channels are not in regulation. mode selection and frequency synchronization the mode/sync pin is a multipurpose pin which provides mode selection and frequency synchronization. connect- ing this pin to v in enables burst mode operation, which provides the best low current ef? ciency at the cost of a higher output voltage ripple. connecting this pin to ground selects pulse-skipping mode, which provides the lowest output ripple, at the cost of low current ef? ciency. the ltc3548 can also be synchronized to another ltc3548 by the mode/sync pin. during synchronization, the mode is set to pulse-skipping and the top switch turn-on is syn- chronized to the rising edge of the external clock. checking transient response the regulator loop response can be checked by look- ing at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second- order overshoot/dc ratio cannot be used to determine phase margin. in addition, a feed-forward capacitor, c f , can be added to improve the high frequency response, as shown in figure 2. capacitor c f provides phase lead by creating a high frequency zero with r2, which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a re- view of control loop theory, refer to application note 76. in some applications, a more severe transient can be caused by switching loads with large (>1f) load input capacitors. the discharged load input capacitors are ef- fectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed speci? cally for this purpose and usually incorporates current limiting, short- circuit protection, and soft-starting. ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. percent ef? ciency can be expressed as: % ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of applications information hot swap is a trademark of linear technology corporation.
ltc3548 11 3548fc the losses in ltc3548 circuits: 1) v in quiescent current, 2) switching losses, 3) i 2 r losses, 4) other losses. 1. the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small (<0.1%) loss that increases with v in , even at no load. 2. the switching current is the sum of the mosfet driver and control currents. the mosfet driver current re- sults from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continuous mode, i gatechg = f o (q t + q b ), where q t and q b are the gate charges of the internal top and bottom mosfet switches. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 3. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current ? ows through inductor l, but is chopped between the internal top and bottom switches. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (d) as follows: r sw = (r ds(on)top )(d) + (r ds(on)bot )(1 C d) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance character- istics curves. thus, to obtain i 2 r losses: i 2 r losses = (i out ) 2 (r sw + r l ) 4. other hidden losses such as copper trace and inter- nal battery resistances can account for additional ef- ? ciency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse re- sistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. thermal considerations in a majority of applications, the ltc3548 does not dis- sipate much heat due to its high ef? ciency. however, in applications where the ltc3548 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches will turn off and the sw node will become high impedance. to prevent the ltc3548 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t rise = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t rise + t ambient as an example, consider the case when the ltc3548 is in dropout on both channels at an input voltage of 2.7v with a load current of 400ma and 800ma and an ambi- ent temperature of 70c. from the typical performance characteristics graph of switch resistance, the r ds(on) resistance of the main switch is 0.425. therefore, power dissipated by each channel is: p d = (i out ) 2 ? r ds(on) = 272mw and 68mw the ms package junction-to-ambient thermal resistance, ja , is 45c/w. therefore, the junction temperature of the regulator operating in a 70c ambient temperature is approximately: t j = (0.272 + 0.068) ? 45 + 70 = 85.3c which is below the absolute maximum junction tempera- ture of 125c. applications information
ltc3548 12 3548fc design example as a design example, consider using the ltc3548 in an portable application with a li-ion battery. the battery pro- vides a v in = 2.8v to 4.2v. the load requires a maximum of 800ma in active mode and 2ma in standby mode. the output voltage is v out = 2.5v. since the load still needs power in standby, burst mode operation is selected for good low load ef? ciency. first, calculate the inductor value for about 30% ripple current at maximum v in : l 2.5v 2.25mhz ? 240ma ?1? 2.5v 4.2v ? ? ? ? ? ? = 1.9h choosing a vendor?s closest inductor value of 2.2h, results in a maximum ripple current of: i l = 2.5v 2.25mhz ? 2.2 h ?1 ? 2.5v 4.2v ? ? ? ? ? ? = 204ma for cost reasons, a ceramic capacitor will be used. c out selection is then based on load step droop instead of esr requirements. for a 5% output droop: c out 2.5 800ma 2.25mhz ? (5% ? 2.5v) = 7.1f a good standard value is 10f. since the output impedance of a li-ion battery is very low, c in is typically 10f. the output voltage can now be programmed by choosing the values of r1 and r2. to maintain high ef? ciency, the current in these resistors should be kept small. choosing 2a with the 0.6v feedback voltage makes r1~300k. a close standard 1% resistor is 280k, and r2 is then 887k. the por pin is a common drain output and requires a pull- up resistor. a 100k resistor is used for adequate speed. figure 3 shows the complete schematic for this design example. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3548. these items are also illustrated graphically in the layout diagram of figure 4. check the following in your layout: 1. does the capacitor c in connect to the power v in (pin 3) and gnd (exposed pad) as close as possible? this capacitor provides the ac current to the internal power mosfets and their drivers. 2. are the c out and l1 closely connected? the (C) plate of c out returns current to gnd and the (C) plate of c in . 3. the resistor divider, r1 and r2, must be connected between the (+) plate of c out and a ground sense line terminated near gnd (exposed pad). the feedback sig- nals v fb should be routed away from noisy components and traces, such as the sw line (pins 4 and 7), and its trace should be minimized. 4. keep sensitive components away from the sw pins. the input capacitor c in and the resistors r1 to r4 should be routed away from the sw traces and the inductors. 5. a ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the gnd pin at one point and should not share the high current path of c in or c out . 6. flood all unused areas on all layers with copper. flood- ing with copper will reduce the temperature rise of power components. these copper areas should be connected to v in or gnd. applications information
ltc3548 13 3548fc low ripple buck regulators using ceramic capacitors run2 v in v in = 2.5v to 5.5v v out2 = 1.8v at 400ma v out1 = 1.2v at 800ma run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3548 c1 10f r5 100k power-on reset c4, 33pf c5, 68pf l1 4.7h l2 10h r4 887k r2 604k r1 604k r3 442k c3 10f c2 10f 3548 ta03 c1, c2, c3: tdk c2012x5r0j106m l1: sumida cdrh2d18/hp-4r7nc l2: sumida cdrh2d18/hp-100nc load current (ma) efficiency (%) 10 100 1000 3548 ta03b 100 95 90 85 80 75 70 65 60 55 50 1.8v 1.2v v in = 3.3v pulse skip mode no load on other channel e e s lod curret fure 4. ltc3548 lout drm (see bord lout cest) run2 v in v in v out2 v out1 run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3548 c in c4 c5 l1 l2 r4 r2 r1 r3 c out2 c out1 3548 f04 bold lines indicate high current paths run2 v in v in = 2.5v* to 5.5v v out2 = 2.5v* at 400ma v out1 = 1.8v at 800ma run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3548 c1 10f r5 100k power-on reset c4, 33pf c5, 68pf l1 2.2h l2 4.7h r4 887k r2 604k r1 301k r3 280k c3 4.7f c2 10f 3548 f03 c1, c2, c3: taiyo yuden jmk212bj106mg c3: taiyo yuden jmk212bj475mg l1: murata lqh32cn2r2m11 l2: murata lqh32cn4r7m23 *v out connected to v in for v in 2.8v (dropout) figure 3. ltc3548 typical application applications information typical applications
ltc3548 14 3548fc typical applications run2 v in v in = 3.6v to 5.5v v out2 = 3.3v at 400ma v out1 = 1.8v at 800ma run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3548 c1* 10f r5 100k power-on reset c4, 33pf c5, 68pf l1 2.2h l2 4.7h r4 887k r2 604k r1 301k r3 196k c3 4.7f c2 10f 3548 ta07 c1, c2: murata grm219r60j106ke19 c3: murata grm219r60j475ke19 l1: coiltronics lpo3310-222mx l2: coiltronics lpo3310-472mx *if c1 is greater than 3" from power source, additional capacitance may be required. 1mm pro? le core and i/o supplies ef? ciency vs load current load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3548 ta08 3.3v 1.8v v in = 5v burst mode operation no load on other channel dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev b) 3.00 p 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom viewexposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.125 typ 2.38 p 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd) dfn rev b 0309 0.25 p 0.05 2.38 p 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p 0.05 (2 sides) 2.15 p 0.05 0.50 bsc 0.70 p 0.05 3.55 p 0.05 package outline 0.25 p 0.05 0.50 bsc package description
ltc3548 15 3548fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description mse package 10-lead plastic msop , exposed die pad (reference ltc dwg # 05-08-1664 rev c) msop (mse) 0908 rev c 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 p 0.152 (.193 p .006) 0.497 p 0.076 (.0196 p .003) ref 8 9 10 10 1 7 6 3.00 p 0.102 (.118 p .004) (note 3) 3.00 p 0.102 (.118 p .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 o C 6 o typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 2.083 p 0.102 (.082 p .004) 2.794 p 0.102 (.110 p .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.83 p 0.102 (.072 p .004) 2.06 p 0.102 (.081 p .004) 0.1016 p 0.0508 (.004 p .002) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref
ltc3548 16 3548fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 0709 rev c ? printed in usa related parts typical application part number description comments ltc1878 600ma (i out ), 550khz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.7v to 6v, v out(min) = 0.8v, i q = 10a, i sd < 1a, msop-8 package lt1940 dual output 1.4a (i out) , constant 1.1mhz, high ef? ciency step-down dc/dc converter v in : 3v to 25v, v out(min) = 1.2v, i q = 2.5ma, i sd = < 1a, tssop-16e package ltc3252 dual 250ma (i out ), 1mhz, spread spectrum inductorless step-down dc/dc converter 88% ef? ciency, v in : 2.7v to 5.5v, v out(min) = 0.9v to 1.6v, i q = 60a, i sd < 1a, dfn-12 package ltc3405/ltc3405a 300ma (i out ), 1.5mhz, synchronous step-down dc/dc converters 96% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 20a, i sd < 1a, thinsot package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous step-down dc/dc converters 96% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20a, i sd < 1a, thinsot package lt3407/lt3407-2 600ma/1.5mhz, 800ma/2.25mhz dual synchronous step-down dc/dc converter 96% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd < 1a, mse, dfn package ltc3411 1.25a (i out ), 4mhz, synchronous step down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd < 1a, msop-10 package ltc3412 2.5a (i out ), 4mhz, synchronous step down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd < 1a, tssop-16e package ltc3414 4a (i out ), 4mhz, synchronous step down dc/dc converter 95% ef? ciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd < 1a, tssop-28e package ltc3440 600ma (i out ), 2mhz, synchronous buck-boost dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 2.5v, i q = 25a, i sd < 1a, msop-10 package load current (ma) 1 efficiency (%) 90 80 70 60 50 40 30 10 100 1000 3548 ta05 v out = 3.3v burst mode operation no load on other channel 4.2v 2.8v 3.6v load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3548 ta06 v out = 1.8v burst mode operation no load on other channel 4.2v 2.8v 3.6v ef? ciency vs load current ef? ciency vs load current run2 v in v in = 2.8v to 4.2v v out2 = 3.3v at 100ma v out1 = 1.8v at 800ma run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3548 c1 10f r5 100k power-on reset c4, 33pf c5, 22pf l1 2.2h l2 15h r4 887k r2 604k r1 301k r3 196k c3 4.7f c6 22f c2 10f 3548 ta04 + m1 d1 c1, c2: taiyo yuden jmk316bj106ml c3: murata grm21br60j475ka11b c6: kemet c1206c226k9pac d1: philips pmeg2010 l1: murata lqh32cn2r2m33 l2: toko a914byw-150m (d52lc series) m1: siliconix si2302ds 2mm height lithium-ion single inductor buck-boost regulator and a buck regulator

▲Up To Search▲

Price & Availability of LTC3548IDDTRPBF

	To Download LTC3548IDDTRPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .